I have run across a few possible errors in the Atmel Datasheets for the AtMega168 and AtMega644. Can anyone please tell me if these are really errors, or if I misunderstand?
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On page 46, a note states that “The test is performed using … BODLEVEL = 101 and BODLEVEL = 101 for Atmega48/88/168.” Should one of these be “BODLEVEL = 110”, or is the second one redundant? |
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On page 253, bit 6 of the ADCSRB register is shown to be ACME. This bit is not documented further. What is the ACME bit of the ADCSRB register? |
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The revision of the document I am reading is listed on the bottom of every page as “Rev. 2545F-AVR-06/05”, while on page 352, it is listed as “Rev. 2545F-AVR-05/05.” Is this inconsistent?
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In the Table of Contents at the end of the datasheet, on page v, there seems to be an error in the spacing of a page number. |
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On page 33, Table 15 contains a value for the “Crystal Oscillator Clock Frequency” of “0 - 16kHz”. Should this be “0 – 20 MHz”? |
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On page 37, the SMCR register is described as having SE as bit 0, and then described as having SE as bit 1. Is this inconsistent?
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On page 40, the PRR register is described as having bit 4 either used as PRUSART0 or as reserved. Is this inconsistent?
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On page 61, the PCIFR register is listed as having both bit 3 and bit 2 named “PCIF2”. Should bit 3 be named “PCIF3”? |
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On page 244, bit 6 of the ADCSRB register is listed as ACME, but it does not seem to be documented further. What is the ACME bit of the ADCSRB registers? |
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On page 290, in figure 132, TQFP-100 and TQFP-64 packages are mentioned. On pages 2 and 3, the packages listed are PDIP 40 and TQFP 44. Do the AtMega164/324/644 come in TQFP-100 or TQFP-64 packages?
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